As technology nodes shrink, semiconductor devices such as a metal-oxide-semiconductor field-effect transistors (MOSFETs) are scaled down and the number of devices of an integrated circuit (IC) increase. Thus, the spacing between gates structures of the ICs decrease (e.g., the pitch in an array of gates becomes tighter). In a method to form such an IC, a dielectric layer such as an inter-level dielectric (ILD) is formed on the substrate and fills in the regions between adjacent gates. However, when an arrangement of gates becomes denser and has a smaller spacing, the ILD layer often cannot effectively fill in the regions between the adjacent gate structures. For example, voids may be formed in the ILD layer. Furthermore, alignment of contacts to the gate structure and/or other transistor features such as a source/drain region may become more difficult as the devices are scaled down. A via used to form a contact may be offset such that an etching process etches through a source/drain region (e.g., low-dose drain) region. This can induce junction leakage.